FPGA Engineer at Bolt Graphics
United States
$150k - $220k
<meta><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:12pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;"><b><strong style="font-size:12pt;white-space:pre-wrap;">About the role:</strong></b></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:12pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;"><span style="color:rgb(0,0,0);background-color:rgb(255,255,255);font-size:12pt;white-space:pre-wrap;">We are</span><span style="white-space:pre-wrap;"> </span><span style="color:rgb(0,0,0);background-color:rgb(255,255,255);font-size:12pt;white-space:pre-wrap;">seeking a highly skilled FPGA Engineer who is fluent in System Verilog and is an expert user of Xilinx (acquired by AMD) FPGAs.</span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:12pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;"><br></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:12pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;"><b><strong style="font-size:12pt;white-space:pre-wrap;">What you'll do:</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Develop and design FPGA systems using System Verilog</span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Debug / Troubleshoot issues in the design</span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Utilize Xilinx</span><span style="white-space:pre-wrap;"> </span><span style="font-size:12pt;white-space:pre-wrap;">Vivado</span><span style="white-space:pre-wrap;"> </span><span style="font-size:12pt;white-space:pre-wrap;">for FPGA development</span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Set up and analyze signals using ILA for debugging purposes</span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Document RTL using standard practices</span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Communicate with team members across different time zones</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:12pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;"><b><strong style="font-size:12pt;white-space:pre-wrap;">Qualifications:</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:3px 0px;font-size:12pt;line-height:1.6;--listitem-marker-color:#000000;--listitem-marker-background-color:#ffffff;letter-spacing:0.25px;"><span style="white-space:pre-wrap;">Bachelors, Masters in Computer Engineering, Electrical Engineering, or equivalent.</span><span style="color:rgb(0,0,0);background-color:rgb(255,255,255);font-size:12pt;white-space:pre-wrap;"> </span></li><li style="margin:3px 0px;font-size:12pt;line-height:1.6;--listitem-marker-color:#000000;--listitem-marker-background-color:#c6c6c6;letter-spacing:0.25px;"><span style="white-space:pre-wrap;">Programming: System Verilog, C/C++</span></li><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Experience with the Xilinx Versal platform</span><span style="white-space:pre-wrap;"> </span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Experience with the Xilinx Alveo platform</span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Experience with QSFP+ fiber communication and encoding strategies</span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Experience with waveform analysis for debugging and optimization</span><span style="white-space:pre-wrap;"> </span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Experience with GTY/GTM</span><span style="white-space:pre-wrap;"> </span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Experience with using and creating custom interfaces using</span><span style="white-space:pre-wrap;"> </span><span style="font-size:12pt;white-space:pre-wrap;">AXI protocol </span><span style="white-space:pre-wrap;"> </span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Experience with fixing timing violations through constraints and logic critical path analysis</span><span style="white-space:pre-wrap;"> </span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Ability to create testbenches to verify functionality of RTL</span><span style="white-space:pre-wrap;"> </span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Advanced debugging features and signal analysis via ILA.</span><span style="white-space:pre-wrap;"> </span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Ability to read technical documents/standards and design hardware to follow those standards </span><span style="white-space:pre-wrap;"> </span></li></ul><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="margin:0px;font-size:12pt;letter-spacing:0.25px;line-height:1.6;"><span style="font-size:12pt;white-space:pre-wrap;">Startup experience</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;"><br></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:12pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;"><b><strong style="font-size:12pt;white-space:pre-wrap;">Compensation Range:</strong></b><span style="font-size:12pt;white-space:pre-wrap;"> $150,000–$220,000 per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.</span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:12pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;"><b><strong style="color:rgb(34,34,35);font-size:12pt;white-space:pre-wrap;">Benefits:</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(32,32,34);margin:3px 0px;font-size:12pt;line-height:1.6;letter-spacing:0.25px;"><span style="color:rgb(32,32,34);font-size:12pt;white-space:pre-wrap;">Medical, Dental, & Vision - 100% covered premiums</span></li><li style="color:rgb(32,32,34);margin:3px 0px;font-size:12pt;line-height:1.6;letter-spacing:0.25px;"><span style="color:rgb(32,32,34);font-size:12pt;white-space:pre-wrap;">Equity - Stock Options</span></li><li style="color:rgb(32,32,34);margin:3px 0px;font-size:12pt;line-height:1.6;letter-spacing:0.25px;"><span style="color:rgb(32,32,34);font-size:12pt;white-space:pre-wrap;">401(k) match</span></li><li style="color:rgb(32,32,34);margin:3px 0px;font-size:12pt;line-height:1.6;letter-spacing:0.25px;"><span style="color:rgb(32,32,34);font-size:12pt;white-space:pre-wrap;">WFH Hardware</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:12pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;"><br></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:12pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;"><i><em style="color:rgb(34,34,35);font-size:12pt;white-space:pre-wrap;">Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.</em></i></p>
Apply Now