ASIC Power Engineer, Principal at Positron Corporation
United States
$200k - $300k
<meta><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:0pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Role Overview</strong></b></h2><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px 11.25pt;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">This role owns power architecture, estimation, optimization, and verification across Positron's AI accelerator roadmap. You will define power methodology from architectural modeling through silicon validation, ensuring industry-leading performance-per-watt while meeting aggressive power and thermal constraints.</span></p><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:0pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Key Responsibilities</strong></b></h2><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Power Architecture & Strategy</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Own the overall chip power strategy, defining approaches for dynamic power, leakage, clock power, memory power, interconnect power, SerDes power, idle power, and peak power.</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Power Modeling</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Develop accurate power models across the full development lifecycle, from early architectural estimation through RTL and gate-level estimation.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Perform vector-based and activity-driven power analysis to validate estimates against real workload behavior.</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Power Optimization</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Drive power optimization techniques including clock gating, operand isolation, power gating, voltage islands, and multi-Vt optimization.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Apply memory, pipeline, toggle-reduction, and data-movement optimization techniques, including approaches tailored to AI workloads.</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Power Integrity</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Partner with the backend team on IR drop, electromigration (EM), power distribution, and power grid planning.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Define power-on sequencing, power domains, reset sequencing, isolation, retention, and UPF/CPF specifications.</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Power Verification</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Own power-aware simulation and UPF verification.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Lead reset verification, low-power state validation, wakeup validation, and power sequencing verification.</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Cross-Functional Collaboration</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Partner closely with Architecture, RTL, Backend, Firmware, Thermal, Packaging, and System Engineering teams to align power decisions across the full chip development flow.</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">AI-Enabled Engineering</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Use AI-driven tools to improve power analysis, regression triage, power anomaly detection, activity clustering, and identification of optimization opportunities.</span></li></ul><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:11.25pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Required Qualifications</strong></b></h2><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">12+ years of ASIC design experience.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Deep expertise in low-power design techniques and methodologies.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Hands-on experience with UPF/CPF power specification and verification flows.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Expert-level proficiency with PrimePower and Joules or equivalent power analysis tools.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Strong background working with advanced process nodes.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">A solid grasp of RTL design and its impact on chip power.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Proven experience achieving aggressive power targets in production silicon.</span></li></ul><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:11.25pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Preferred Qualifications</strong></b></h2><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Experience with AI accelerator architectures.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Familiarity with LPDDR and HBM memory interfaces.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Working knowledge of PCIe.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Experience with dynamic voltage and frequency scaling (DVFS).</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Exposure to thermal modeling.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Hands-on experience with silicon power validation.</span></li></ul><h3 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:21pt;font-weight:600;letter-spacing:0.25px;margin-top:12pt;margin-bottom:12pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:14pt;white-space:pre-wrap;">Leveling & Scope</strong></b></h3><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px 11.25pt;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.</span></p><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:0pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">What Success Looks Like</strong></b></h2><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px 11.25pt;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Success in this role looks like power estimates that consistently predict silicon behavior, sustained performance-per-watt leadership across Positron's product line, and a power architecture that is reused and extended across future generations of chips.</span></p><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:0pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Why Join Us?</strong></b></h2><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Shape the power architecture foundation for a new generation of AI inference accelerators, with direct influence on Positron's performance-per-watt leadership.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Work at the frontier of silicon and AI, on chips built specifically for the demands of large-scale LLM inference.</span></li></ul><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:11.25pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Compensation & Benefits</strong></b></h2><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">The base salary range for this role is $200,000 – $300,000.</span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;"> </span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.</span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;"> </span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px 11.25pt;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.</span></p><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:0pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Benefits & Perks</strong></b></h2><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">We want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.</span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Health and wellness</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Fully company-paid medical, dental, and vision insurance for you and your dependents</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Company-paid life and disability coverage, with voluntary options to add more</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Supplemental hospital, critical illness, and accident coverage available</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Time off and flexibility</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Unlimited paid time off, we encourage everyone to truly unplug and recharge</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">13 paid company holidays</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Remote-first culture with a company-provided computer and home office setup</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Compensation and future</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Competitive salary and equity</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">401(k) with company matching, eligible from day one</span></li></ul><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:11.25pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Visa Support</strong></b></h2><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.</span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;"> </span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Equal Opportunity Employer.</strong></b><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;"> If you're excited about the role but don't meet every bullet, we'd still love to hear from you.</span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;"><br></p>
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