Mid-End ASIC Engineer, Principal at Positron Corporation
United States
$190k - $280k
<meta><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:0pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Role Overview</strong></b></h2><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px 11.25pt;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">We're looking for an exceptional Principal Mid-End ASIC Engineer to own synthesis, timing convergence, implementation readiness, and logical design quality across our AI accelerator roadmap. This is a deeply technical, hands-on engineering role responsible for transforming high-quality RTL into implementation-ready netlists while driving timing closure strategy, constraint development, physical-aware optimization, and close collaboration between RTL designers and backend implementation partners. You will serve as the technical bridge between architecture, RTL, verification, and physical implementation.</span></p><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:0pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Key Responsibilities</strong></b></h2><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Synthesis Methodology & Ownership</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Define and own synthesis methodology across current and future ASIC generations, including scalable flows for RTL synthesis, constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Establish signoff criteria and methodology for synthesis deliverables.</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Hands-On Synthesis & Constraint Development</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Own hands-on synthesis using industry-leading EDA tools, including Cadence Genus and Synopsys Design Compiler (or equivalent).</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Develop and maintain SDC constraints, clock definitions, false paths, multicycle paths, generated clocks, and MMMC environments.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Drive continuous improvement of synthesis QoR.</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Timing Closure Leadership</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Own logical timing closure and drive optimization across frequency, area, power, congestion, and wireability.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Perform root-cause analysis of timing bottlenecks and develop timing budgets across all chip partitions.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Collaborate closely with architecture and RTL teams to eliminate timing risks before physical implementation.</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Physical-Aware Optimization</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Partner closely with backend implementation engineers to drive physical-aware synthesis, retiming, register balancing, pipeline optimization, logic restructuring, and hierarchical timing budgeting.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Ensure RTL is implementation-friendly from the outset.</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Cross-Functional Execution</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Partner closely with architecture, RTL, verification, physical design, DFT, IP providers, and backend design services to drive rapid issue resolution.</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Vendor Technical Leadership</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Serve as Positron's synthesis technical lead with external implementation partners, reviewing QoR, timing, area reports, and constraint methodology, and defining acceptance criteria.</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">AI-Enabled Engineering</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Apply AI to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation.</span></li></ul><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:11.25pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Required Qualifications</strong></b></h2><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">12+ years of ASIC implementation experience, including multiple successful tapeouts.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Expert-level proficiency in synthesis methodology and flow development.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Deep expertise in timing closure across complex, multi-million-gate designs.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Expert-level command of Cadence Genus and/or Synopsys Design Compiler.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Strong SDC expertise, including constraint development and MMMC environments.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">A solid grasp of RTL design principles and implementation-friendly coding practices.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Hands-on experience with advanced process nodes at 5nm and below.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Strong Tcl and Python scripting ability for automation and flow development.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Excellent debugging and root-cause analysis skills.</span></li></ul><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:11.25pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Preferred Qualifications</strong></b></h2><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Experience with AI accelerators, CPUs, or GPUs.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Familiarity with LPDDR, PCIe, or SerDes interfaces.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Exposure to chiplet-based architectures and multi-clock SoC designs.</span></li></ul><h3 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:21pt;font-weight:600;letter-spacing:0.25px;margin-top:12pt;margin-bottom:12pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:14pt;white-space:pre-wrap;">Leveling & Scope</strong></b></h3><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px 11.25pt;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.</span></p><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:0pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">What Success Looks Like</strong></b></h2><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px 11.25pt;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Within one year, this person will have established a production-grade synthesis methodology, delivered predictable timing closure, reduced implementation iterations, produced high-quality implementation-ready RTL, and built a scalable methodology to support future ASIC generations.</span></p><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:0pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Why Join Us?</strong></b></h2><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Play a foundational role in shaping the synthesis and timing closure methodology for next-generation AI inference accelerators.</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Work at the cutting edge of AI hardware, directly influencing chips built to power frontier AI workloads.</span></li></ul><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:11.25pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Compensation & Benefits</strong></b></h2><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">The base salary range for this role is $190,000 – $280,000.</span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;"> </span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.</span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;"> </span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px 11.25pt;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.</span></p><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:0pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Benefits & Perks</strong></b></h2><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">We want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.</span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Health and wellness</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Fully company-paid medical, dental, and vision insurance for you and your dependents</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Company-paid life and disability coverage, with voluntary options to add more</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Supplemental hospital, critical illness, and accident coverage available</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Time off and flexibility</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Unlimited paid time off — we encourage everyone to truly unplug and recharge</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">13 paid company holidays</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Remote-first culture with a company-provided computer and home office setup</span></li></ul><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Compensation and future</strong></b></p><ul data-pattern="discCircleSquare" data-depth="1" style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;"><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Competitive salary and equity</span></li><li style="color:rgb(0,0,0);margin:0pt 0px;font-size:11pt;line-height:1.2;letter-spacing:0.25px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">401(k) with company matching, eligible from day one</span></li></ul><h2 style="font-family:"Basel Grotesk",Arial,sans-serif;line-height:1.2;font-size:29pt;font-weight:600;letter-spacing:0.5px;margin-top:11.25pt;margin-bottom:11.25pt;padding-left:0px;"><b><strong style="color:rgb(0,0,0);font-size:18pt;white-space:pre-wrap;">Visa Support</strong></b></h2><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.</span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;"> </span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.2;letter-spacing:0.25px;margin:0pt 0px;padding:0px;"><b><strong style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;">Equal Opportunity Employer.</strong></b><span style="color:rgb(0,0,0);font-size:11pt;white-space:pre-wrap;"> If you're excited about the role but don't meet every bullet, we'd still love to hear from you.</span></p><p style="font-family:"Basel Grotesk",Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;"><br></p>
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